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Deep neural networks increasingly rely on smooth, non-monotonic activation functions such as the Gaussian Error Linear Unit (GELU), which has become the default activation in modern transformer and convolutional architectures. While GELU improves accuracy, its exact form involves the Gaussian error function, which is expensive to evaluate in hardware, so deploying such models on resource-constrained edge devices demands a hardware-efficient yet accurate approximation. This work presents the design and FPGA implementation of the GELU activation function using Verilog HDL. The proposed architecture adopts a hybrid CORDIC–polynomial approximation: a lightweight polynomial datapath performs the cubic pre-shaping (x + 0.044715x³) and the √(2/π) scaling, while a pipelined hyperbolic-CORDIC core evaluates the hyperbolic tangent without dedicated multipliers. The complete design uses Q7.25 signed fixed-point arithmetic and a finite-state-machine controller, and is realised as a reconfigurable accelerator supporting GELU, ReLU, and SILU. Following a hardware–software co-design methodology, a bit-accurate Python golden model is used to study quantization and to verify the Verilog implementation, after which the design is synthesised and implemented on the Xilinx Artix-7 (XC7A35T) device of the Basys 3 board using Xilinx Vivado. Functional verification over the input range [−3, +3] shows a maximum absolute error of approximately 1.3 × 10⁻⁴with respect to the ideal GELU. The implemented accelerator consumes 2157 look-up tables (10%), 1856 flip-flops (4%), and 18 DSP slices (20%), dissipates a total on-chip power of 0.182 W, and meets timing at a 100 MHz clock with a positive worst-negative slack of 0.083 ns (maximum frequency ≈ 100.8 MHz). These results demonstrate accurate, low-power, and area-efficient activation computation suitable for real-time neural-network inference in edge-AI and biomedical applications.